Conventional frequency synthesizers generally include a phase locked loop (PLL). A PLL is a device which generates an output frequency that is a function of a reference frequency. When implemented in a device such as a wireless transceiver, the output frequency of the PLL changes frequently. For example, the output frequency of the PLL changes at start-up and when changing channels. In each of these situations, it is desirable for the PLL to settle as quickly as possible. Further, in frequency hopping spread spectrum (FHSS) transceivers, the output frequency of the PLL changes for each frequency hop. Thus, the PLL is required to have an even faster settling time in order to comply with the timing requirements of the frequency hopping transceiver.
In conventional PLL's there is a trade off between settling time and phase noise, which are both a function of the bandwidth of a low-pass filter in the PLL. Thus, a designer may be forced to select a bandwidth for the low-pass filter that meets the phase noise requirements while providing a less than desirable settling time. Thus, there remains a need for a frequency synthesizer that avoids the tradeoff between settling time and phase noise and that has a reduced settling time.